A Region-Driven Analysis of Processor Power Consumption for Various HPC Workloads

	International Journal of P2P Network Trends and Technology (IJPTT)
	© 2019 by IJPTT Journal
	Volume-9 Issue-1
	Year of Publication : 2019
	Authors : Sharda Dixit, Amarjeet Sharma, Anil Gupta
	DOI :  10.14445/22492615/IJPTT-V9I1P404

Citation

MLA Style: Sharda Dixit, Amarjeet Sharma, Anil Gupta "A Region-Driven Analysis of Processor Power Consumption for Various HPC Workloads" International Journal of P2P Network Trends and Technology 9.1 (2019): 13-20.

APA Style:Sharda Dixit, Amarjeet Sharma, Anil Gupta (2019). A Region-Driven Analysis of Processor Power Consumption for Various HPC Workloads. International Journal of P2P Network Trends and Technology, 9(1), 13-20.

Abstract

Power consumption is one of the significant challenges for present and future HPC systems. The processor is one of the most power-hungry components at the node level of an HPC cluster. Various features are already implemented in processor hardware and OS/kernel, which optimize power consumption at the node level. We performed several experiments on a variety of workloads and observed power consumption patterns for CPU, memory and IO intensive regions of workloads. The investigations focused on correlating the CPU utilization, memory access, idle state residency, clock gated residency, and power consumption. Our results show that the scope of reducing energy consumed by workload, using employing frequency scaling, for compute-intensive workloads, is slim at the system software level.

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Keywords
DVFS, Clock-Gating, C-State, P-State