Low Power High Speed Two’s Complement Multiplier

International Journal of P2P Network Trends and Technology (IJPTT)          
© 2013 by IJPTT Journal
Volume-3 Issue-3                           
Year of Publication : 2013
Authors : P.Arulbalaji, Mrs. K.Vanitha


P.Arulbalaji, Mrs. K.Vanitha."Low Power High Speed Two’s Complement Multiplier". International Journal of P2P Network Trends and Technology (IJPTT), V3(3):8 - 13 May - Jun 2013, ISSN:2249-2615, www.ijpttjournal.org. Published by Seventh Sense Research Group.


To reduce the area of partial product array size and improve the speed which is generated by a radix-4 Modified Booth Encoded Multiplier is used. This reduction is possible without any increase in the delay of the partial product generation stage. This reduction provides faster compression of the partial product array and regular layouts in two’s complement multiplier. The proposed method is that the Radix-4 (Fixed-Width) Modified Booth Multipliers are used to achieve the low power and increase the speed by modifying the partial product matrix size. The Multiplier design implemented using Xilinx. The results based on a rough theoretical analysis and on logic synthesis showed its efficiency in terms of both area and delay. It is compared with Radix-4 (short bit-width) Modified booth encoded Multiplier.


[1] J.Y. Kang and J.L. Gaudiot, “A Simple High-Speed Multiplier Design”, IEEE Trans. on Computers, vol. 55, no. 10, pp. 1253-1258, Oct.2006.
[2] W.C. Yeh and C.W. Jen, “High-Speed Booth Encoded Parallel Multiplier Design”, IEEE Trans. on Computers, vol. 49, no. 7, pp. 692-701, July 2000.
[3] F. Lamberti, N. Andrics, E.Antelo, and P.Mountuchi, “Speeding – Up Booth Encoded Multipliers by Reducing the size of Partial Product Array”, internal report, http://arith.polito.it/it_mbe.pdf pp. 1-14, 2009.
[4] K. J. Cho, K. C. Lee, J. G. Chung, and K. K. Parhi, “Design of low-error fixed-width modified Booth multiplier,” IEEE Trans. Very Large Scale Integration. (VLSI) Syst., vol. 12, no. 5, pp. 522–531, May 2004.
[5] XLINX Synthesis and Simulation Design Guide. http://www.xilinx.com/itp/xilinx10/books/docs/sim/sim.pdf


- Multiplication, Modified Booth Encoding, partial product array, Fixed-width Modified Booth multiplier.